Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

摘要

This communication shows the influence of clocking schemes on thedigital switching noise generation. It will be shown how the choice of a suitedclocking scheme for the digital part reduces the switching noise, thus alleviatingthe problematic associated to limitations of performances in mixed-signalAnalog/Digital Integrated Circuits. Simulation data of a pipelined XOR chainusing both a single-phase and a two-phase clocking schemes, as well as of two nbitcounters with different clocking styles lead, as conclusions, to recommendmultiple clock-phase and asynchronous styles for reducing switching noise.